Effect of Gate Structure on the Trapping Behavior of GaN Junctionless FinFETs
DC Field | Value | Language |
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dc.contributor.author | Im, Ki-Sik | - |
dc.contributor.author | An, Sung Jin | - |
dc.contributor.author | Theodorou, Christoforos G. | - |
dc.contributor.author | Ghibaudo, Gerard | - |
dc.contributor.author | Cristoloveanu, Sorin | - |
dc.contributor.author | Lee, Jung-Hee | - |
dc.date.available | 2021-04-29T08:41:25Z | - |
dc.date.created | 2020-10-05 | - |
dc.date.issued | 2020-06 | - |
dc.identifier.issn | 0741-3106 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/kumoh/handle/2020.sw.kumoh/19078 | - |
dc.description.abstract | We investigated the performances of GaN junctionless fin-shaped field-effect transistors (FinFETs) with two different types of gate structures; overlapped-and partially covered-gate. DC, low-frequency noise (LFN), and pulsed I-V characterization measurements were performed and analyzed together in order to identify the conduction mechanism and examine both the interface and buffer traps in the devices. The fabricated GaN junctionless device with overlapped-gate structure exhibits improved DC and noise performance compared to the device with partially covered-gate, even though its gate length is much larger. The LFN behavior was found to be dominated by carrier number fluctuations (CNF). At off-state, the device with partially covered-gate exhibits generation-recombination (g-r) noise on top of 1/f noise. This superposition is correlated with the severe current collapse revealed by pulsed I-V measurements. In contrast, the device with overlapped-gate shows clear 1/f behavior without g-r noise. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Effect of Gate Structure on the Trapping Behavior of GaN Junctionless FinFETs | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | An, Sung Jin | - |
dc.identifier.doi | 10.1109/LED.2020.2991164 | - |
dc.identifier.wosid | 000541155300010 | - |
dc.identifier.bibliographicCitation | IEEE ELECTRON DEVICE LETTERS, v.41, no.6, pp.832 - 835 | - |
dc.relation.isPartOf | IEEE ELECTRON DEVICE LETTERS | - |
dc.citation.title | IEEE ELECTRON DEVICE LETTERS | - |
dc.citation.volume | 41 | - |
dc.citation.number | 6 | - |
dc.citation.startPage | 832 | - |
dc.citation.endPage | 835 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | LOW-FREQUENCY NOISE | - |
dc.subject.keywordPlus | PERFORMANCE | - |
dc.subject.keywordAuthor | GaN junctionless | - |
dc.subject.keywordAuthor | FinFET | - |
dc.subject.keywordAuthor | low-frequency noise | - |
dc.subject.keywordAuthor | generation-recombination noise | - |
dc.subject.keywordAuthor | current collapse | - |
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