Hardware Architecture to Extract Feature Points for Object Recognition

Abstract

The object recognition is applied to mobile devices and home appliances recently. Accordingly, The SIFT algorithm draws attention for feature point extraction. However, since its process needs excessive amount of computations and memory accesses, SIFT is not a suitable algorithm to implement in software for real-time embedded applications. To solve this problem, we propose a method to implement the SIFT algorithm efficiently. The method changes the computation order to preferentially compute the pixel values required to filter the input image. The second step is that FIFO buffers are used to save next computation images in advance and parallelism is achieved to concurrently perform filtering the images with all Gaussian filters that have different variance values. Finally, the method concurrently subtracts these generated Gaussian images. As a result, this hardware can extract feature points on qVGA(320x240) image in real-time. The proposed hardware is implemented with the Virtex4-LX60 FPGA and the performance is 111fps at 206MHz.