Second-order Incremental Delta-sigma Modulator with 3-bit SAR ADC and Capacitor Sharing Scheme

Abstract

A small area and low power second-order incremental delta-sigma modulator (DSM) using a cascade of integrators with feedforward architecture is proposed for sensor interface applications. To reduce the area of capacitors, the proposed second-order incremental DSM uses a 3-bit successive approximation register (SAR) analog-to- digital converter (ADC) and capacitor sharing scheme. It is designed using a 180-nm CMOS process with a supply of 1.8 V. The simulated SNDR of the designed second-order incremental DSM is about 106.2 dB for an input signal with a frequency of 100.0 Hz at an over sampling ratio of 512. The area and power consumption are 0.1484 mm(2) and 145.8 mu W, respectively.