Hardware Accelerated Design on Bag of Words Classification Algorithm

Abstract

In this paper, we propose an image retrieval algorithm for real-time processing and design it ashardware. The proposed method is based on the classification of BoWs(Bag of Words) algorithm andproposes an image search algorithm using bit stream. K-fold cross validation is used for theverification of the algorithm. Data is classified into seven classes, each class has seven images and atotal of 49 images are tested. The test has two kinds of accuracy measurement and speed measurement. The accuracy of the image classification was 86.2% for the BoWs algorithm and 83.7% the proposedhardware-accelerated software implementation algorithm, and the BoWs algorithm was 2.5% higher. The image retrieval processing speed of BoWs is 7.89s and our algorithm is 1.55s. Our algorithm is5.09 times faster than BoWs algorithm. The algorithm is largely divided into software and hardwareparts. In the software structure, C-language is used. The Scale Invariant Feature Transform algorithmis used to extract feature points that are invariant to size and rotation from the image. Bit streams aregenerated from the extracted feature point. In the hardware architecture, the proposed image retrievalalgorithm is written in Verilog HDL and designed and verified by FPGA and Design Compiler. Thegenerated bit streams are stored, the clustering step is performed, and a searcher image databases oran input image databases are generated and matched. Using the proposed algorithm, we can improveconvenience and satisfaction of the user in terms of speed if we search using database matchingmethod which represents each object.