The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors
- Authors
- Ok, Seung-Ho; Lee, Yong-Hwan; Shim, Jae Hoon; Lim, Sung Kyu; Moon, Byungin
- Issue Date
- Feb-2017
- Publisher
- MDPI
- Keywords
- through-silicon via; stereo matching processor; technology scaling; low-power
- Citation
- SENSORS, v.17, no.2
- Journal Title
- SENSORS
- Volume
- 17
- Number
- 2
- URI
- https://scholarworks.bwise.kr/kumoh/handle/2020.sw.kumoh/22538
- DOI
- 10.3390/s17020426
- ISSN
- 1424-8220
1424-8220
- Abstract
- Recently, stereo matching processors have been adopted in real-time embedded systems such as intelligent robots and autonomous vehicles, which require minimal hardware resources and low power consumption. Meanwhile, thanks to the through-silicon via (TSV), three-dimensional (3D) stacking technology has emerged as a practical solution to achieving the desired requirements of a high-performance circuit. In this paper, we present the benefits of 3D stacking and process technology scaling on stereo matching processors. We implemented 2-tier 3D-stacked stereo matching processors with GlobalFoundries 130-nm and Nangate 45-nm process design kits and compare them with their two-dimensional (2D) counterparts to identify comprehensive design benefits. In addition, we examine the findings from various analyses to identify the power benefits of 3D-stacked integrated circuit (IC) and device technology advancements. From experiments, we observe that the proposed 3D-stacked ICs, compared to their 2D IC counterparts, obtain 43% area, 13% power, and 14% wire length reductions. In addition, we present a logic partitioning method suitable for a pipeline-based hardware architecture that minimizes the use of TSVs.
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