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고속 얼라인먼트 마커 인식을 위한 개선된 방식의 FPGA 구현FPGA Implementation of an Enhanced Method for High-Speed Alignment Marker Recognition

Other Titles
FPGA Implementation of an Enhanced Method for High-Speed Alignment Marker Recognition
Authors
김현용정해
Issue Date
2019
Publisher
대한전기학회
Keywords
Integral Histogram; Alignment Marker; Template Matching; Candidate Clustering
Citation
전기학회 논문지 P권, v.68, no.2, pp 69 - 75
Pages
7
Journal Title
전기학회 논문지 P권
Volume
68
Number
2
Start Page
69
End Page
75
URI
https://scholarworks.bwise.kr/kumoh/handle/2020.sw.kumoh/23632
ISSN
1229-800x
Abstract
Alignment marker recognition is a widely used machine vision technology in production processes, and its core technology is to recognize a marker or a unique pattern rapidly and detect the angle and position of them. However, many small and medium-sized enterprises use imported equipments because they have no ability to implement them with low cost. The objective of this paper provides their necessary solution that processes recognition within 80 ms by using a low specification FPGA. To recognize the maker rapidly, an improved integral histogram with the limited mask size is proposed. Finally, we verify that the proposed algorithm detects the similarity and position of the marker by comparing the clustering among candidates within the limited time.
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