A Single-Bit 2nd-Order Delta-Sigma Modulator with 10-μm Column-Pitch for a Low Noise CMOS Image Sensor
- Authors
- 권민우; 천지민
- Issue Date
- 2020
- Publisher
- 한국정보전자통신기술학회
- Keywords
- Analog-to-digital converter; CIFF; CMOS image sensor; column-parallel ADC array; delta-sigma modulator
- Citation
- 한국정보전자통신기술학회 논문지, v.13, no.1, pp 8 - 16
- Pages
- 9
- Journal Title
- 한국정보전자통신기술학회 논문지
- Volume
- 13
- Number
- 1
- Start Page
- 8
- End Page
- 16
- URI
- https://scholarworks.bwise.kr/kumoh/handle/2020.sw.kumoh/23656
- ISSN
- 2005-081X
2288-9302
- Abstract
- In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for column-parallel analog-to-digital converter (ADC) array used in a low noise CMOS image sensor. The proposed modulator implements two switched capacitor integrators and a single-bit comparator within only 10-μm column-pitch for column-parallel ADC array. Also, peripheral circuits for driving all column modulators include a non-overlapping clock generator and a bias circuit. The proposed delta-sigma modulator has been implemented in a 110-nm CMOS process. It achieves 88.1-dB signal-to-noise-and-distortion ratio (SNDR), 88.6-dB spurious-free dynamic range (SFDR), and 14.3-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 418 for 12-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 970⨯10 μm2 and 248 μW, respectively.
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