Multi-Level Memory Comprising Low-Temperature Poly-Silicon and Oxide TFTs
- Authors
- Kim, Jongbin; Chung, Hoon-Ju; Lee, Seung-Woo
- Issue Date
- Jan-2021
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Thin film transistors; Transistors; Programming; Random access memory; Silicon; Logic gates; Leakage currents; Thin-film transistor (TFT); multi-level memory; low-temperature polycrystalline silicon and oxide (LTPO)
- Citation
- IEEE ELECTRON DEVICE LETTERS, v.42, no.1, pp 42 - 45
- Pages
- 4
- Journal Title
- IEEE ELECTRON DEVICE LETTERS
- Volume
- 42
- Number
- 1
- Start Page
- 42
- End Page
- 45
- URI
- https://scholarworks.bwise.kr/kumoh/handle/2020.sw.kumoh/25887
- DOI
- 10.1109/LED.2020.3037059.
- ISSN
- 0741-3106
1558-0563
- Abstract
- In this letter, a new multi-level memory cell using low-temperature polycrystalline silicon and oxide (LTPO) thin-film transistor (TFT) backplane is proposed. The multi-bit data storage can be achieved with a simple structure of two transistors and a capacitor, which controls the threshold voltage of a memory cell transistor exactly. In a memory cell, the low-temperature polycrystalline silicon (LTPS) TFT provides excellent stability against bias stress or current stress. In addition, the oxide semiconductor TFT enables the long-term data storage by virtue of its extremely low off-state leakage current. The proposed memory is fabricated with the LTPO TFT process which includes p-type LTPS and n-type oxide TFTs. Furthermore, the implementation of the multi-level property is successfully verified by measured results.
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Collections - School of Electronic Engineering > 1. Journal Articles
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