A 1.8 V 40-MS/sec 10-bit 0.18-µm CMOS Pipelined ADC using a Bootstrapped Switch with Constant Resistance
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 어지훈 | - |
dc.contributor.author | 장영찬 | - |
dc.contributor.author | 김상훈 | - |
dc.contributor.author | 김문규 | - |
dc.date.available | 2020-04-24T13:25:28Z | - |
dc.date.created | 2020-03-31 | - |
dc.date.issued | 2012 | - |
dc.identifier.issn | 2234-8255 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/kumoh/handle/2020.sw.kumoh/2686 | - |
dc.description.abstract | A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-µm 1-poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 mm2 and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | 한국정보통신학회 | - |
dc.title | A 1.8 V 40-MS/sec 10-bit 0.18-µm CMOS Pipelined ADC using a Bootstrapped Switch with Constant Resistance | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | 장영찬 | - |
dc.identifier.bibliographicCitation | Journal of Information and Communication Convergence Engineering, v.10, no.1, pp.85 - 90 | - |
dc.citation.title | Journal of Information and Communication Convergence Engineering | - |
dc.citation.volume | 10 | - |
dc.citation.number | 1 | - |
dc.citation.startPage | 85 | - |
dc.citation.endPage | 90 | - |
dc.type.rims | ART | - |
dc.identifier.kciid | ART001650165 | - |
dc.description.journalClass | 2 | - |
dc.subject.keywordAuthor | Pipelined | - |
dc.subject.keywordAuthor | Analog to digital converter | - |
dc.subject.keywordAuthor | Bootstrapped switch | - |
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