Effects of Contact Potential and Sidewall Surface Plane on the Performance of GaN Vertical Nanowire MOSFETs for Low-Voltage Operation

Abstract

GaN-based materials are expected to show excellent immunity against short-channel effects because they have relatively lower permittivity and higher electron effective mass, compared to other materials such as Si, Ge, and In(Ga)As. To further reduce the short-channel effects, it is important to enhance the gate controllability of the device by utilizing a gate-all-around (GAA) structure. In this article, GaN vertical GAA nanowire MOSFETs with various diameters of 120, 75, and 45 nm have been fabricated. The device with a diameter of 120 nm shows a threshold voltage of 0.7 V, drain saturation voltage of 0.5 V, and subthreshold swing of 70 mV/decade, which would be suitable for low-voltage/power applications. However, the devices with smaller diameters of 75 and 45 nm show peculiar characteristics, such as a second rise of the drain current in output characteristics and a negative transconductance.