FPGA-based Inference Parallelization for Onboard RL-based Routing in Dynamic LEO Satellite NetworksFPGA-based Inference Parallelization for Onboard RL-based Routing in Dynamic LEO Satellite Networks
- Other Titles
- FPGA-based Inference Parallelization for Onboard RL-based Routing in Dynamic LEO Satellite Networks
- Authors
- 김도형; 이현철; 원동식; 한명훈
- Issue Date
- Jul-2024
- Publisher
- 한국항공우주학회
- Keywords
- Heterogeneous processor; Parallelization; Deep reinforcement learning
- Citation
- International Journal of Aeronautical and Space Sciences, v.25, no.3, pp 1135 - 1145
- Pages
- 11
- Journal Title
- International Journal of Aeronautical and Space Sciences
- Volume
- 25
- Number
- 3
- Start Page
- 1135
- End Page
- 1145
- URI
- https://scholarworks.bwise.kr/kumoh/handle/2020.sw.kumoh/28776
- DOI
- 10.1007/s42405-024-00720-w
- ISSN
- 2093-274X
2093-2480
- Abstract
- This paper addresses the problem of onboard computer application of dynamic low-orbit satellite network routing algorithms. In low-orbit satellite networks, the satellite topology changes in real time, and satellite disconnection occurs frequently. The problem of routing algorithms for low-orbit satellites can be solved by reinforcement learning algorithms. However, the inference process based on deep reinforcement learning models suffers from excessive computation due to the operation of multiple convolutional layers. In this paper, we propose a method to accelerate convolutional layer operations by parallelizing them using heterogeneous processors. This approach is compared to the traditional single-processor-based convolutional operation method, commonly used in dynamic low-orbit satellite network routing algorithms. Our evaluation, conducted on an actual heterogeneous processor-based onboard computer, demonstrates that the proposed method not only matches the accuracy of the conventional single-processor-based approach, but also significantly reduces the execution time.
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