Experimental observation of zero DIBL in short-channel hysteresis-free ferroelectric-gated FinFET
- Authors
- Shin, J[Shin, Jaemin]; Shin, C[Shin, Changhwan]
- Issue Date
- Mar-2019
- Publisher
- PERGAMON-ELSEVIER SCIENCE LTD
- Keywords
- Short-channel transistor; Negative capacitance; Drain-induced-barrier-lowering; Ferroelectric material
- Citation
- SOLID-STATE ELECTRONICS, v.153, pp.12 - 15
- Indexed
- SCIE
SCOPUS
- Journal Title
- SOLID-STATE ELECTRONICS
- Volume
- 153
- Start Page
- 12
- End Page
- 15
- URI
- https://scholarworks.bwise.kr/skku/handle/2021.sw.skku/10788
- DOI
- 10.1016/j.sse.2018.12.012
- ISSN
- 0038-1101
- Abstract
- The experimental investigation for the drain-induced-barrier-lowering (DIBL) in nanometer scale hysteresis-free 100 nm-long ferroelectric-gated FinFET (which employs the voltage-amplifying attribute of Pb(Zr0.52Ti0.48)O-3-based ferroelectric capacitor) is done to verify the DIBL improvement. The DIBL of the ferroelectric-gated FinFET (which is evaluated at 10(-7) A/mu m of drain current) is improved from similar to 48 mV/V to similar to 32 mV/V. When the DIBL is evaluated at 10(-6) A/mu m, it is reduced from 22.89 mV/V to similar to 0 mV/V. The physical origin of the DIBL enhancement can be understood due to negative DIBL. The negative DIBL effect [a.k.a., drain-induced-barrier-rising (DIBAR)] is originated from a decrease of internal gate voltage, which takes place due to a gate charge reduction with increased drain voltage.
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Collections - Information and Communication Engineering > School of Electronic and Electrical Engineering > 1. Journal Articles
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