Design of a Fault Detection Circuit for One-Time Programmable Memories for Reducing Time

Abstract

As memory becomes more versatile, testing to detect defects becomes important. Defect testing occurs at various stages of the device's lifecycle to ensure proper functionality and to verify that it meets the specifications determined by the customer. Having a circuit built into the circuit itself to detect faults can ensure accurate and reliable behavior, and eliminate the need for special equipment for testing, reducing costs and saving time. Accordingly, this paper proposes a circuit that can quickly and accurately detect faults in One-Time Programmable (OTP) Memory. The work has been implemented on a TSMC 55nm CMOS process and the OTP Memory is a 256X32bits One Time Programmable Device used in the TSMC 55nm process from eMemory Technology Inc. © 2023 IEEE.