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Comparative study of novel u-shaped SOI FinFET against multiple-fin bulk/SOI FinFETopen access

Authors
Son, M.[Son, Myoungsu]Sung, J.[Sung, Juho]Baac, H.W.[Baac, Hyoung Won]Shin, C.[Shin, Changhwan]
Issue Date
2023
Publisher
Institute of Electrical and Electronics Engineers Inc.
Keywords
Device design; FinFET; FinFETs; Logic gates; Performance evaluation; Semiconductor process modeling; Silicon; SOI FinFET; Three-dimensional displays; Transconductance; u-FinFET
Citation
IEEE Access, v.11, pp.1 - 1
Indexed
SCIE
SCOPUS
Journal Title
IEEE Access
Volume
11
Start Page
1
End Page
1
URI
https://scholarworks.bwise.kr/skku/handle/2021.sw.skku/108248
DOI
10.1109/ACCESS.2023.3308592
ISSN
2169-3536
Abstract
Superior scalability and better gate-to-channel capacitive coupling can be achieved with adopting gate-all-around (GAA) device architecture. However, compared against FinFET device structure, the GAA device is not very cost-effective. In addition, its yield for mass production is not as high as expected. In order to explore the device design option for extending the current FinFET device out, we have come up with a new idea, i.e., novel device structure to increase the effective channel width without affecting the contact poly pitch (CPP). A novel u-FinFET structure is a type of FinFET that has a u-shaped channel. By using 3-D TCAD simulation, it turned out that the u-FinFET (vs. conventional bulk/SOI FinFETs) shows a 27.3% higher drain current at <italic>V</italic>GS = 0.7 V because of its 28.7% wider effective channel width. Especially, the u-FinFET can be adopted for high performance applications because it can implement a wider channel width for a given layout area. Moreover, taking advantages of using the current processes and materials for bulk/SOI FinFET, the u-FinFET can be fabricated (which must be very cost-effective). Hence, with taking advantages of using the u-FinFET structure, the current FinFET platform would last more. Author
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