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Study on the Circuit Performance of Various Interconnect Metal Materials in the Latest Process Nodes
- Authors
- Choi, M.[Choi, Moonjeong]; Park, J.[Park, Juhwan]; Choi, S.[Choi, Seoungyeol]; Kwon, K.[Kwon, Kyungbae]; Lee, Y.[Lee, Yeji]; Jang, W.[Jang, Wonyeong]; Jeon, J.[Jeon, Jongwook]
- Issue Date
- Aug-2023
- Publisher
- Institute of Electronics Engineers of Korea
- Keywords
- benchmark; Gate-all-around FET; interconnect; parasitic extraction; process design kit
- Citation
- Journal of Semiconductor Technology and Science, v.23, no.4, pp.215 - 227
- Indexed
- SCIE
SCOPUS
KCI
- Journal Title
- Journal of Semiconductor Technology and Science
- Volume
- 23
- Number
- 4
- Start Page
- 215
- End Page
- 227
- ISSN
- 1598-1657
- Abstract
- In this work, circuit-level benchmarks were performed on Copper(Cu), Tungsten(W), Cobalt(Co), Ruthenium(Ru), and Doped-multilayer-graphene (DMLG), which are various metallic material options applicable to the wire process at the late semiconductor process nodes. For the transistor, a multi-nanosheet field-effect-transistor (mNS-FET) with gate-all-around (GAA) technology was used, and the power and performance characteristics of the inverter ring oscillator circuit were analyzed assuming a 3 nm process node. In addition, various wire metal options for circuit layout were evaluated by varying fan-out number and wire length. As a result, the speed is fastest for Co and the speed reduction is smallest for DMLG in FO1 50CPP. © 2023, Institute of Electronics Engineers of Korea. All rights reserved.
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