K-Band Hetero-Stacked Differential Cascode Power Amplifier with High Psat and Efficiency in 65 nm LP CMOS Technologyopen access
- Authors
- Choi, KJ[Choi, Kyu-Jin]; HYUN, P. J.[HYUN, PARK JAE]; Kim, SK[Kim, Seong-Kyun]; Kim, BS[Kim, Byung-Sung]
- Issue Date
- Apr-2021
- Publisher
- MDPI
- Keywords
- power amplifier; CMOS; K-band; stacked power amplifier; cascode amplifier
- Citation
- ELECTRONICS, v.10, no.8
- Indexed
- SCIE
SCOPUS
- Journal Title
- ELECTRONICS
- Volume
- 10
- Number
- 8
- URI
- https://scholarworks.bwise.kr/skku/handle/2021.sw.skku/1252
- DOI
- 10.3390/electronics10080890
- ISSN
- 2079-9292
- Abstract
- A K-band complementary metal-oxide-semiconductor (CMOS) differential cascode power amplifier is designed with the thin-oxide field effect transistor (FET) common source (CS) stage and thick-oxide FET common gate (CG) stage. Use of the thick-oxide CG stage affords the high supply voltage to 3.7 V and enables the high output power. Additionally, simple analysis shows that the gain degradation due to the low cut-off frequency of the thick-oxide CG FET can be compensated by the high output resistance of the thick-oxide FET if the inter-stage node is neutralized. The measured results of the proposed power amplifier demonstrate the saturated output power of the 23.3 dBm with the 31.3% peak power added efficiency (PAE) at 24 GHz frequency. The chip is fabricated in 65-nm low power (LP) CMOS technology and the chip size including all pads is 700 mu m x 630 mu m.
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Collections - Information and Communication Engineering > Department of Semiconductor Systems Engineering > 1. Journal Articles
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