A Highly Linear Neuromorphic Synaptic Device Based on Regulated Charge Trap/Detrap
- Authors
- Choi, J.-M.[Choi, J.-M.]; Park, E.-J.[Park, E.-J.]; Woo, J.-J.[Woo, J.-J.]; Kwon, K.-W.[Kwon, K.-W.]
- Issue Date
- Nov-2019
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Keywords
- charge trap; CMOS-compatible; floating gate; incremental step pulse programming (ISPP); linear programming; synaptic device
- Citation
- IEEE Electron Device Letters, v.40, no.11, pp.1848 - 1851
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE Electron Device Letters
- Volume
- 40
- Number
- 11
- Start Page
- 1848
- End Page
- 1851
- URI
- https://scholarworks.bwise.kr/skku/handle/2021.sw.skku/13839
- DOI
- 10.1109/LED.2019.2943113
- ISSN
- 0741-3106
- Abstract
- In this letter, we present highly linear potentiation/depression behaviors of a neuromorphic synaptic device made of CMOS-compatible floating gate (FG) cells. The kinetics of the charge trap/detrap mechanism under various pulse shapes are analyzed to design a simple 2C-4T FG cell with a modulated column write driver for embedded incremental step pulse programming (ISPP) via analog feedback. Utilizing real-time ISPP, the linearity and symmetry of the weight update were significantly improved due to the content-aware programming strength. Moreover, the proposed circuit technique provides flexibility regarding the size of the program/erase steps in addition to the superior linearity. The proposed FG cells with peripheral circuits are fabricated using 180nm CMOS technology and exhibited a differential non-linearity (DNL) less than 0.946 least significant bit (LSB) with 100 weight states. The excellent linearity remains unchanged even when the directions of potentiation/depression are reversed throughout the entire range. © 1980-2012 IEEE.
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Collections - Information and Communication Engineering > Department of Semiconductor Systems Engineering > 1. Journal Articles
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