The demonstration of S2P (Serial-to-parallel) converter with address allocation method using 28 nm CMOS technology

Abstract

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 µm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz. © 2021 by the authors. Licensee MDPI, Basel, Switzerland.