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A 10-bit 1 MS/s segmented Dual-Sampling SAR ADC with reduced switching energy
- Authors
- Rikan, BS[Rikan, Behnam Samadpoor]; Abbasizadeh, H[Abbasizadeh, Hamed]; Park, YJ[Park, Young-Jun]; Kang, HY[Kang, Hye-Yeong]; Kim, S[Kim, SangYun]; Pu, Y[Pu, YoungGun]; Lee, M[Lee, Minjae]; Hwang, KC[Hwang, Keum Cheol]; Yang, Y[Yang, Youngoo]; Lee, KY[Lee, Kang-Yoon]
- Issue Date
- Dec-2017
- Publisher
- ELSEVIER SCI LTD
- Keywords
- SAR ADC; Dual-Sampling; Segmented capacitive DAC; Trimming bit
- Citation
- MICROELECTRONICS JOURNAL, v.70, pp.89 - 96
- Indexed
- SCIE
SCOPUS
- Journal Title
- MICROELECTRONICS JOURNAL
- Volume
- 70
- Start Page
- 89
- End Page
- 96
- ISSN
- 0026-2692
- Abstract
- This paper implements a 10-bit segmented Dual-Sampling SAR ADC for a WPT system. To solve the mid-code problem of the Dual-Sampling structure and improve the linearity, a segmented structure is adopted in capacitive DAC. A new switching scheme is proposed for MSBs decisions to skip some of the unnecessary switching steps. This ADC is applied to digitize analog inputs of the different sub-blocks of the WPT system. Applying these techniques reduces the unit capacitor size, as well as the power consumption while improving the linearity of the system. The overall system achieves 9.8 ENOB at 1 MS/s conversion speed and consumes 19.6 mu A from 3 V supply voltage. DNL and INL for this structure are measured to be -0.63-0.56 and -0.85-0.79 LSB respectively. The active area of the ADC in 0.18 mu m CMOS process is 760 x 430 mu m(2).
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Related Researcher
- YANG, YOUNGOO
- Information and Communication Engineering (Electronic and Electrical Engineering)