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A design of 10-bit, 10 MS/s Pipelined ADC with Time-interleaved SAR
- Authors
- Jang, B.[Jang, B.]; Hayder, A.S.[Hayder, A.S.]; Do, S.[Do, S.]; Cho, S.[Cho, S.]; Lee, D.[Lee, D.]; Pu, Y.[Pu, Y.]; Hwang, K.C.[Hwang, K.C.]; Yang, Y.[Yang, Y.]; Lee, K.-Y.[Lee, K.-Y.]
- Issue Date
- Apr-2017
- Publisher
- ELSEVIER SCI LTD
- Keywords
- Pipelined ADC; Time-interleaved SAR; Multiplying DAC
- Citation
- MICROELECTRONICS JOURNAL, v.62, pp.79 - 84
- Indexed
- SCIE
SCOPUS
- Journal Title
- MICROELECTRONICS JOURNAL
- Volume
- 62
- Start Page
- 79
- End Page
- 84
- ISSN
- 0026-2692
- Abstract
- This paper presents a 10-bit, 10 MS/s pipelined ADC with a time-interleaved SAR. Owing to the shared multiplying-DAC between the flash ADC and the multi-channel-SAR ADC, the total capacitance of the SAR ADC is decreased by 93.75%. The proposed ADC architecture can therefore provide a higher resolution than the conventional time-interleaved flash-SAR ADC. The proposed 10-bit, 10 MS/s ADC achieves a 9.318-bit ENOB and a figure-of-merit of 357.11 fJ/conversion-step. The ADC that consumes 2.28 mW under a supply voltage of 1.2 V was fabricated in 0.13 mu m CMOS and occupies an area of only 0.21 mm(2).
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Related Researcher
- HWANG, KEUM CHEOL
- Information and Communication Engineering (Electronic and Electrical Engineering)