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Work-in-progress: Balanced cache bypassing for critical warp reduction
- Issue Date
- 2017
- Publisher
- Association for Computing Machinery, Inc
- Citation
- Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion, CASES 2017
- Journal Title
- Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion, CASES 2017
- ISSN
- 0000-0000
- Abstract
- Warp-level cache bypassing has been proposed to resolve GPU memory resource contention on GPU computing. However, the proposed cache bypassing scheme has sub-optimal performance due to warp criticality problem in balanced workload. In this paper, we show that warp-level cache bypassing is a sub-optimal solution and propose a balanced cache bypassing scheme to solve this problem. © 2017 ACM.
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Related Researcher
- HAN, HWAN SOO
- Computing and Informatics (Computer Science and Engineering)