A New Test Method for Bit Line Disturbance Leakage Current in Dynamic Random Access Memory

Abstract

This work proposes a new test algorithm for detecting bit line disturbed weak cells in dynamic random access memory (DRAM). The basic idea of the proposed test algorithm is to test using the voltage difference between the storage node and the bit line during the read operation of the first word line. This voltage difference is generated by a sense amplifier using the data background of the first word line cells. The proposed test method has a precision of 99% compared with conventional test method for detecting weak cells. In addition, it can also determine whether the leakage path is the cell's own bit line or a neighboring bit line. This classification helps to determine the physical locations of failed cells, enabling precise physical failure analysis.