Roles of Residual Stress in Dynamic Refresh Failure of a Buried-Recessed-Channel-Array Transistor (B-CAT) in DRAM
- Authors
- Park S.[Park S.]; Seo H.[Seo H.]; Oh J.[Oh J.]; Kim I.[Kim I.]; Hong H.[Hong H.]; Jin G.[Jin G.]; Roh Y.[Roh Y.]
- Issue Date
- Jul-2016
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- B-CAT; Dynamic Refresh; Failure; Fowler-Nordheim tunneling; Grain Growth; Hole Trapping; Residual Stress; Si-O-Si bond breaking; TiN
- Citation
- IEEE ELECTRON DEVICE LETTERS, v.37, no.7, pp.859 - 861
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE ELECTRON DEVICE LETTERS
- Volume
- 37
- Number
- 7
- Start Page
- 859
- End Page
- 861
- URI
- https://scholarworks.bwise.kr/skku/handle/2021.sw.skku/36150
- DOI
- 10.1109/LED.2016.2563159
- ISSN
- 0741-3106
- Abstract
- We clarify the role of metal gates (e.g., TiN) on the degradation of the state-of-the-art buried-channel-array transistor (B-CAT) in dynamic random access memory (DRAM) chips. Unless the thermal budget during the processing step for integration is well controlled, residual stress caused by grain growth of the metal gate can result in a dynamic refresh failure of B-CAT through the negative shift in threshold voltage (-Delta Vth). A hole trapping model is proposed to explain this phenomenon. Uncontrolled grain growth of the metal gate increases the residual stress level on SiO2, and, consequently, it breaks the strained Si-O-Si bonds, which can serve as precursor sites for incoming holes. Residual stress in the three-dimensional transistor architecture, therefore, must be well controlled to improve the reliability of commercial DRAM chips.
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Collections - Information and Communication Engineering > School of Electronic and Electrical Engineering > 1. Journal Articles
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