Low Noise, Low Power 5-channel Sonar Signal Conditioning Receiver with 1.5 MS/s-12.5 MS/s 16-bit Sigma-delta ADC for Ocean Acoustic Measurements
- Authors
- Jo, Jong-Wan; Shehzad, Khuram; Verma, Deeksha; Kim, Sung-Jin; Park, Young-Woo; Kim, Kwan-Tae; Kim, Sang-Yun; Pu, YoungGun; Yang, Young-Goo; Hwang, Keum-Cheol; Lee, Dong-Hun; Kim, Hyung-Moon; Lee, Kang-Yoon
- Issue Date
- Aug-2020
- Publisher
- IEEK PUBLICATION CENTER
- Keywords
- Sigma-delta ADC; low noise; band pass filter; sonar sensor; receiver; parallel-to-serial interface
- Citation
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.20, no.4, pp 326 - 342
- Pages
- 17
- Indexed
- SCIE
SCOPUS
KCI
- Journal Title
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
- Volume
- 20
- Number
- 4
- Start Page
- 326
- End Page
- 342
- URI
- https://scholarworks.bwise.kr/skku/handle/2021.sw.skku/3636
- DOI
- 10.5573/JSTS.2020.20.4.326
- ISSN
- 1598-1657
2233-4866
- Abstract
- This paper presents the design of a 5-channel receiver for ocean acoustic measurement in very noisy environments. When measuring distances in the ocean through sonar, the input signal level to the receiver can change drastically depending on the distance between the transmitter and objects. Thus, a receiver with low sensitivity and a wide dynamic range is proposed in this work. In order to minimize the Input-Referred (IR) noise for the high sensitivity of the receiver, a low noise pre-amplifier is proposed and implemented, ultimately achieving a noise of 29.6 nV/root z at 50 kHz. In addition, a Sigma-Delta Analogto-Digital Converter (SD ADC) with variable sampling rates is proposed by using the clock splitting technique in the Sigma-Delta Modulator (SDM) core. In addition, the decimation factor of the digital filter placed after the SDM in the SD ADC can be controlled so as to reduce the power consumption. Through the use of these techniques in the SD ADC, we can implement reconfigurable sampling rates from 1.5 MS/s to 12.5 MS/s with low power consumption. In order to overcome the limitation of the number of pins for multi-channel application, a Parallel-to-Serial (P2S) interface is proposed and designed in the receiver. The 5-channel receiver in this paper is implemented in a 0.18 mu m CMOS process and the die area is 14.44 mm2. The total power consumption of this chip under a supply voltage of 2.4 V is 46.8 mW. The measured sensitivity and dynamic range are 100 dBV and 100 dB, respectively. The measured SNDR at the output of the SD ADC is 82.02 dB when the input signal frequency and sampling frequency are 7 kHz and 6.25 Msps, respectively. The maximum phase error between five channels is measured to be +/- 0.8 degrees.
- Files in This Item
- There are no files associated with this item.
- Appears in
Collections - Information and Communication Engineering > School of Electronic and Electrical Engineering > 1. Journal Articles
![qrcode](https://api.qrserver.com/v1/create-qr-code/?size=55x55&data=https://scholarworks.bwise.kr/skku/handle/2021.sw.skku/3636)
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.