Non-Alloyed Ohmic Contacts on GaAs Using Metal-Interlayer-Semiconductor Structure With SF6 Plasma Treatment
- Authors
- Kim, SH[Kim, Seung-Hwan]; Kim, GS[Kim, Gwang-Sik]; Kim, SW[Kim, Sun-Woo]; Kim, JK[Kim, Jeong-Kyu]; Choi, C[Choi, Changhwan]; Park, JH[Park, Jin-Hong]; Choi, R[Choi, Rino]; Yu, HY[Yu, Hyun-Yong]
- Issue Date
- Apr-2016
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Contact resistance; Fermi-level unpinning; gallium arsenide; SF6 plasma; passivation
- Citation
- IEEE ELECTRON DEVICE LETTERS, v.37, no.4, pp.373 - 376
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE ELECTRON DEVICE LETTERS
- Volume
- 37
- Number
- 4
- Start Page
- 373
- End Page
- 376
- URI
- https://scholarworks.bwise.kr/skku/handle/2021.sw.skku/37092
- DOI
- 10.1109/LED.2016.2524470
- ISSN
- 0741-3106
- Abstract
- We demonstrate the effect of SF6 plasma passivation with a ZnO interlayer in a metal-interlayer-semiconductor (MIS) structure to reduce source/drain (S/D) contact resistance. The interface trap states and the metal-induced gap states causing the Fermi-level pinning problem are effectively alleviated by passivating the GaAs surface with SF6 plasma treatment and inserting a thin ZnO interlayer, respectively. Specific contact resistivity exhibits similar to 10(4) x reduction when the GaAs surface is treated with SF6 plasma, followed by ZnO interlayer deposition, compared with the Ti/n-GaAs (similar to 2x10(18) cm(-3)) S/D contact. This result proposes the promising non-alloyed S/D ohmic contact for III-V semiconductor-based transistors.
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Collections - Information and Communication Engineering > School of Electronic and Electrical Engineering > 1. Journal Articles
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