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Robust via-programmable ROM design based on 45nm process considering process variation and enhancement Vmin and yield
- Authors
- Jang, B.-J.[Jang, B.-J.]; Lee, C.-H.[Lee, C.-H.]; Sim, S.-H.[Sim, S.-H.]; Choi, K.-W.[Choi, K.-W.]; Byun, D.-H.[Byun, D.-H.]; Jung, Y.-H.[Jung, Y.-H.]; Park, K.-M.[Park, K.-M.]; Heo, D.-Y.[Heo, D.-Y.]; Kim, G.-H.[Kim, G.-H.]; Yang, J.-S.[Yang, J.-S.]
- Issue Date
- 2015
- Keywords
- 45nm; Robust Design; Vmin; Via-Rom; Yield
- Citation
- Proceedings - IEEE International Symposium on Circuits and Systems, v.2015-July, pp.2541 - 2544
- Journal Title
- Proceedings - IEEE International Symposium on Circuits and Systems
- Volume
- 2015-July
- Start Page
- 2541
- End Page
- 2544
- Abstract
- This paper presents a Via programmable read only memory (Via-ROM) for Vmin and macro-yield enhancement through robust ROM designs based on 45nm process. The main stability issues in ROM are 1) lower on-cell (NMOS) current, 2) higher keeper (PMOS) current, and 3) higher bit-line (BL) parasitic value. To improve the Vmin and macro-yield, the robust ROM design schemes are implemented as follows. 1) ROM bit cell size optimization without increasing a bit cell area, 2) BL loading reduction to use a rom code pattern optimization, 3) selective full BL pre-charge and keeper control to use an external pin named as KCS (Keeper Control Signal) and 4) wide pulse width generator using an asynchronous 3-bit ripple binary counter. These schemes to improve 0 read margin were confirmed by both the simulation and the measurement. Experimental results show that macro-yield improved from 0% to 100% at 1.1V (Voperation) and -40°C. © 2015 IEEE.
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