Hybrid parallelization for HEVC decoder
- Authors
- Jo H.[Jo H.]; Sim D.[Sim D.]; Jeon B.[Jeon B.]
- Issue Date
- 2013
- Keywords
- HEVC; Parallel decoding; Video coding
- Citation
- Proceedings of the 2013 6th International Congress on Image and Signal Processing, CISP 2013, v.1, pp.170 - 175
- Journal Title
- Proceedings of the 2013 6th International Congress on Image and Signal Processing, CISP 2013
- Volume
- 1
- Start Page
- 170
- End Page
- 175
- URI
- https://scholarworks.bwise.kr/skku/handle/2021.sw.skku/62914
- DOI
- 10.1109/CISP.2013.6743980
- Abstract
- This paper presents a new hybrid parallelization method for High Efficiency Video Coding (HEVC) decoder. The proposed method groups HEVC decoding modules into entropy decoding, pixel decoding, and in-loop filtering parts for optimal parallelization considering the characteristic of all the parts. The proposed method employs coding tree unit (CTU)-level 2D wavefront for the pixel decoding part. To decrease the delay between the entropy decoding and pixel decoding, task level parallelism (TLP) is additionally employed for two parts. For the HEVC deblocking filter, CTU-level data level parallelism (DLP) with equally partitioned CTUs is proposed. In addition, CTU row-level DLP for sample adaptive offset (SAO) is proposed to achieve maximum parallel performance and to minimize the overhead of organizing a backup buffer. The experimental results show that the proposed approach for parallel deblocking filter achieved a speed-up of 5.4× and the parallel SAO approach achieved a speed-up of 3.7× maximally on the multi-core platform. Furthermore, the proposed parallel HEVC decoder shows a speed-up of 2.9× with 6 threads without any encoder parallel tools such as wavefront parallel processing (WPP) coding and picture partitioning with tile and slice segments. © 2013 IEEE.
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Collections - Information and Communication Engineering > School of Electronic and Electrical Engineering > 1. Journal Articles
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