Expanding CGA Acceleration Regions Using Compiler-Driven Architecture Extensions

Abstract

Aggressive embedded processors are often equipped with general purpose cores and special purpose acceleration logics. In our paper, we consider a reconfigurable processor that consists of very long instruction word (VLIW) cores and coarse grained arrays (CGAs). CGAs are particularly used to enhance the performance by exploiting loop parallelism, while VLIW cores rely on discovering instruction level parallelism. For time consuming loops, CGAs can accelerate them with powerful pipeline scheduling. However, not all loops can be accelerated by CGAs. Outer loops and loops containing function calls cannot be candidates for CGA acceleration. In our paper, we adopt instruction extensions to convert code fragments in outer loops and simple functions into single instructions. With the extended instructions in CGA, more loops can be accelerated with CGA. In addition, we transform loop structures to include larger regions for CGA acceleration. Our experiment with mpeg2dec and epic from Mediabench shows 44% and 46% performance increases, respectively.