A low power PFD and dual mode CP with small current mismatch for PLL application

Abstract

A high speed Phase-Frequency Detector (PFD) and Charge Pump (CP) are implemented using 0.13μm CMOS process with 1.2 V supply. The PFD is implemented with TSPC (True Single-Phase Clock) and positive edge triggered D flip-flop. Its polarity can be changed by setting the port. The dead zone problem is solved using an additional reset time. A single charge pump is implemented with two compensators. Dual mode CP design makes the charge pump much more flexible in applications. The current mismatch for the two modes is below 4.9 % within the voltage range of from 0.2 to 1.0 V. © (2012) Trans Tech Publications.