An enhancement of via profile using MLR mask

Abstract

The fabrication process of semiconductor is more and more difficult as scaling down. Especially, the via profile formation is one of the main challenges which is suffering from making stable device process because ArF photo resist (PR) itself can not provide proper etch selectivity to sub-layers. Recently, many researches have been studied for the via process in terms of photo property, etch property and process compatibility using bi-layer resist process (BLR), tri-layer resist process (TLR), and multi-layer resist (MLR) process. In this paper, we proposed and demonstrated for beyond 90 nm scaled logic via process consisting of high-k inter metal dielectric (IMD) using multi-layer resist (MLR) organic hard mask. Based on the test results described in this paper, the results show the higher etching selectivity to each layer and also helped to easily control the anisotropic profiles. (C) 2011 Published by Elsevier B.V.