Endurance reliability of multilevel-cell flash memory using a ZrO(2)/Si(3)N(4) dual charge storage layer
- Authors
- Zhang, G[Zhang, Gang]; Hwang, WS[Hwang, Wan Sik]; Lee, SH[Lee, Seung-Hwan]; Cho, BJ[Cho, Byung-Jin]; Yoo, WJ[Yoo, Won Jong]
- Issue Date
- Sep-2008
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Citation
- IEEE TRANSACTIONS ON ELECTRON DEVICES, v.55, no.9, pp.2361 - 2369
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON ELECTRON DEVICES
- Volume
- 55
- Number
- 9
- Start Page
- 2361
- End Page
- 2369
- URI
- https://scholarworks.bwise.kr/skku/handle/2021.sw.skku/80768
- DOI
- 10.1109/TED.2008.927396
- ISSN
- 0018-9383
- Abstract
- The mechanisms of programming/erasing (P/E) and endurance degradation have been investigated for multilevel-cell (MLC) Flash memories using a Si(3)N(4) (NROM) or a ZrO(2)/Si(3)N(4) dual charge storage layer (DCSL). Threshold-voltage (V(th))-level disturbance is found to be the major endurance degradation factor of NROM-type MLCs, whereas separated charge storage and step-up potential wells give rise to a superior V(th)-level controllability for DCSL MLCs. The programmed V(th), levels of DCSL MLCs are controlled by the spatial charge distribution, as well as the charge storage capacity of each storage layer, rather than the charge injection. As a result, DCSL MLCs show negligible V(th)-level offsets (< 0.2 V) that are maintained throughout the 105 P/E cycles, demonstrating significantly improved endurance reliability compared to NROM-type MLCs.
- Files in This Item
- There are no files associated with this item.
- Appears in
Collections - SKKU Advanced Institute of Nano Technology > ETC > 1. Journal Articles
- Graduate School > SKKU Advanced Institute of Nano Technology > 1. Journal Articles
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.