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A 6 Gbps/pin low-power half-duplex active cross-coupled LVDS transceiver with switched termination

Authors
Kim, S[Kim, Sua]Kong, BS[Kong, Bai-Sun]Lee, C[Lee, Chilgee]Kim, C[Kim, Changhyun]Jun, YH[Jun, Young-Hyun]
Issue Date
Aug-2008
Publisher
ELECTRONICS TELECOMMUNICATIONS RESEARCH INST
Keywords
LVDS; half-duplex; transceiver; DRAM; I/O
Citation
ETRI JOURNAL, v.30, no.4, pp.612 - 614
Indexed
SCIE
SCOPUS
KCI
Journal Title
ETRI JOURNAL
Volume
30
Number
4
Start Page
612
End Page
614
URI
https://scholarworks.bwise.kr/skku/handle/2021.sw.skku/81012
DOI
10.4218/etrij.08.0207.0235
ISSN
1225-6463
Abstract
A novel linear switched termination active cross-coupled low-voltage differential signaling (LVDS) transceiver operating at 1.5 GHz clock frequency is presented On the transmitter side, an active cross-coupled linear output driver and a switched termination scheme are applied to achieve high speed with low current On the receiver side, a shared pre-amplifier scheme is employed to reduce power consumption. The proposed LVDS transceiver implemented in an 80 nm CMOS process is successfully demonstrated to provide a data rate of 6 Gbps/pin, an output data window of 147 ps peak-to-peak and a data swing of 196 in V The power consumption is measured to be 4.2 mW/pin at 1.2 V
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Information and Communication Engineering (Semiconductor Systems Engineering)
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