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Design of Frequency Multiplier with Delay Locked Loop that is insensitive to PVT Variation and prescreen Harmonic Lock
- Issue Date
- 2021
- Publisher
- IEEE Computer Society
- Keywords
- Delay Locked Loop; Frequency Multiplier
- Citation
- International Conference on Ubiquitous and Future Networks, ICUFN, v.2021-August, pp.195 - 197
- Indexed
- SCOPUS
- Volume
- 2021-August
- Start Page
- 195
- End Page
- 197
- ISSN
- 2165-8528
- Abstract
- As the wireless network market has been grown, high-performance and efficient communication technology are demanded for devices. Specifically, reference clock signal forms an essential part of designing devices such as wearable one or the Internet of Things. The conventional structure of XOR is used to multiply the reference frequency. The structure of DLL illustrates that how frequency is extracted from application based on various values of desired supply voltage. © 2021 IEEE.
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Related Researcher
- LEE, KANG YOON
- Information and Communication Engineering (Electronic and Electrical Engineering)