Smart Bus Arbiter for QoS control in H.264 decoders
- Authors
- Lee, Chanho
- Issue Date
- Mar-2011
- Publisher
- IEEK PUBLICATION CENTER
- Keywords
- H.264; QoS; implementation; AHB; arbiter; arbitration policy
- Citation
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.11, no.1, pp.33 - 39
- Journal Title
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
- Volume
- 11
- Number
- 1
- Start Page
- 33
- End Page
- 39
- URI
- http://scholarworks.bwise.kr/ssu/handle/2018.sw.ssu/13719
- DOI
- 10.5573/JSTS.2011.11.1.033
- ISSN
- 1598-1657
- Abstract
- H.264 decoders usually have pipeline architecture by a macroblock or a 4 x 4 sub-block. The period of the pipeline is usually fixed to guarantee the operation in the worst case which results in many idle cycles and higher data bandwidth. Adaptive pipeline architecture for H.264 decoders has been proposed for efficient decoding and lower the requirement of the bandwidth for the memory bus. However, it requires a controller for the adaptive priority control to utilize the advantage. We propose a smart bus arbiter that replaces the controller. It is introduced to adjust the priority adaptively the QoS (Quality of Service) control of the decoding process. The smart arbiter can be integrated the arbiter of bus systems and it works when certain conditions are met so that it does not affect the original functions of the arbiter. An H.264 decoder using the proposed architecture is designed and implemented to verify the operation using an FPGA.
- Files in This Item
-
Go to Link
- Appears in
Collections - College of Information Technology > ETC > 1. Journal Articles
![qrcode](https://api.qrserver.com/v1/create-qr-code/?size=55x55&data=https://scholarworks.bwise.kr/ssu/handle/2018.sw.ssu/13719)
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.