반도체 회로 연결선의 신뢰도 해석을 위한 전류 해석 기법

Abstract

As process technology for semiconductor goes beyond the ultra-deep submicrometer regime, interconnect reliability on a chip has become a serious design concern. As process parameters scale, interconnect widths are reduced rapidly while the current flowing through the interconnect does not decrease in a proportional manner. This trend increases current densities in metal interconnects which may lead to poor reliability for electromigration. Hence, it is critical to estimate the current amount passing through the interconnects earlier in semiconductor design stages. The purpose of this paper is to propose a fast yet accurate current estimation technique that can offer not only analysis time equivalent to those offered by the previous approximation methods but also a relatively precise estimation by using closed-form equations. The accuracy of the proposed technique was confirmed to be about 8 times better on average when compared to the previous work.