A Phase-Based Approach for On-Chip Bus Architecture Optimization

Abstract

As the integration scale of a chip increases, on-chip interconnects suffer from the increased area occupied by a large number of bus signals. To reduce the overhead for communication, this paper formulates a new concept of an on-chip communication approach, called phase-based interconnection, with an example protocol, system-on-chip network protocol (SNP). In the phase-based communication, a small number of signals called phase signals are used to distinguish the types of signals transmitted through the main communication channel. To identify transactions transmitted through the channel, the SNP protocol defines the allowed sequence of phases for each transaction. A theoretical framework provides conditions for a phase-based protocol to allow immediate decoding of transactions. Simulation results show that the bandwidth of SNP is greater than that of a de facto standard bus protocol although SNP has wires only about three-fifths of the standard bus protocol. Although the signal-toggling rate is increased because of the multiplexed transmission of various signals through a single communication channel, simulation results show that the increase is not significant for multimedia applications that frequently transmit burst transfers. The phase omission of SNP helps to reduce the transaction failure rate to 65% while the hardware implementation cost for the support of phase omission is negligible.