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A survey of Flash Translation Layer

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dc.contributor.authorChung, Tae-Sun-
dc.contributor.authorPark, Dong-Joo-
dc.contributor.authorPark, Sangwon-
dc.contributor.authorLee, Dong-Ho-
dc.contributor.authorLee, Sang-Won-
dc.contributor.authorSong, Ha-Joo-
dc.date.available2018-05-10T15:19:58Z-
dc.date.created2018-04-17-
dc.date.issued2009-05-
dc.identifier.issn1383-7621-
dc.identifier.urihttp://scholarworks.bwise.kr/ssu/handle/2018.sw.ssu/15840-
dc.description.abstractRecently, flash memory is widely adopted in embedded applications as it has several strong points, including its non-volatility, fast access speed, shock resistance, and low power consumption. However, due to its hardware characteristics, specifically its "erase-before-write" feature, it requires a software layer known as FTL (Flash Translation Layer). This paper surveys the state-of-the-art FTL software for flash memory. It defines the problems, addresses algorithms to solve them, and discusses related research issues. In addition, the paper provides performance results based on our implementation of each FTL algorithm. (C) 2009 Elsevier B.V. All rights reserved.-
dc.publisherELSEVIER SCIENCE BV-
dc.relation.isPartOfJOURNAL OF SYSTEMS ARCHITECTURE-
dc.titleA survey of Flash Translation Layer-
dc.typeArticle-
dc.identifier.doi10.1016/j.sysarc.2009.03.005-
dc.type.rimsART-
dc.identifier.bibliographicCitationJOURNAL OF SYSTEMS ARCHITECTURE, v.55, no.5-6, pp.332 - 343-
dc.description.journalClass1-
dc.identifier.wosid000267390200004-
dc.identifier.scopusid2-s2.0-65849353697-
dc.citation.endPage343-
dc.citation.number5-6-
dc.citation.startPage332-
dc.citation.titleJOURNAL OF SYSTEMS ARCHITECTURE-
dc.citation.volume55-
dc.contributor.affiliatedAuthorPark, Dong-Joo-
dc.type.docTypeArticle; Proceedings Paper-
dc.subject.keywordAuthorFlash memory-
dc.subject.keywordAuthorEmbedded system-
dc.subject.keywordAuthorFile system-
dc.description.journalRegisteredClassscopus-
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