Performance analysis of banyan-type Multistage Interconnection Networks under nonuniform traffic pattern
DC Field | Value | Language |
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dc.contributor.author | Mun, Y | - |
dc.date.available | 2018-05-10T17:39:02Z | - |
dc.date.created | 2018-04-17 | - |
dc.date.issued | 2005-07 | - |
dc.identifier.issn | 0920-8542 | - |
dc.identifier.uri | http://scholarworks.bwise.kr/ssu/handle/2018.sw.ssu/19356 | - |
dc.description.abstract | Multistage Interconnection Networks(MINs) have a number of applications in the areas of computer and communications. The most widely researched structure among MIN's is the (I)banyan type network. It has several variations such as buffered banyan, batcher-banyan, tandem banyan, recirculating banyan and banyan with contention resolution phase. Analytical performance evaluation is crucial for justifying the merit of the design in different operational conditions. While several analytical models have been proposed for the performance evaluation of MINs, they are mainly for uniform traffics. Even the models for nonuniform traffics have several shortcomings such as they only consider output buffered structure or do not consider blocking conditions, In this paper, the more accurate models than any other ones so far have been proposed for the performance evaluation of multibuffered banyan-type MIN's under nonuniform traffic condition is obtained. The accuracy of proposed models are conformed by comparing with the results from simulation. Firstly, single buffer model is developed. Markov chain is used for the analysis. Multibuffer model is obtained from single buffer model. Simulation is performed using Discrete Evenet Simulaton(DES) method. As a results, proposed model proves to be very accurate. | - |
dc.publisher | SPRINGER | - |
dc.relation.isPartOf | JOURNAL OF SUPERCOMPUTING | - |
dc.subject | MULTIPROCESSORS | - |
dc.title | Performance analysis of banyan-type Multistage Interconnection Networks under nonuniform traffic pattern | - |
dc.type | Article | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | JOURNAL OF SUPERCOMPUTING, v.33, no.1-2, pp.33 - 52 | - |
dc.description.journalClass | 1 | - |
dc.identifier.wosid | 000230592400004 | - |
dc.identifier.scopusid | 2-s2.0-18144377802 | - |
dc.citation.endPage | 52 | - |
dc.citation.number | 1-2 | - |
dc.citation.startPage | 33 | - |
dc.citation.title | JOURNAL OF SUPERCOMPUTING | - |
dc.citation.volume | 33 | - |
dc.contributor.affiliatedAuthor | Mun, Y | - |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | Multistage Interconnection Networks | - |
dc.subject.keywordAuthor | nonuniform traffic pattern | - |
dc.subject.keywordPlus | MULTIPROCESSORS | - |
dc.description.journalRegisteredClass | scopus | - |
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