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A Novel Clock Distribution Technique for Asynchronous Pipelined-SFQ Sequential Logic using Variable Delay-controlled JTLs
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 위재경 | - |
| dc.date.available | 2018-06-12T10:16:18Z | - |
| dc.date.created | 2018-06-11 | - |
| dc.date.issued | 2005-10 | - |
| dc.identifier.uri | http://scholarworks.bwise.kr/ssu/handle/2018.sw.ssu/30265 | - |
| dc.title | A Novel Clock Distribution Technique for Asynchronous Pipelined-SFQ Sequential Logic using Variable Delay-controlled JTLs | - |
| dc.type | Conference | - |
| dc.type.rims | CONF | - |
| dc.identifier.bibliographicCitation | International Superconductive Electronics Conference, pp.449 - 455 | - |
| dc.description.journalClass | 1 | - |
| dc.citation.endPage | 455 | - |
| dc.citation.startPage | 449 | - |
| dc.citation.title | International Superconductive Electronics Conference | - |
| dc.contributor.affiliatedAuthor | 위재경 | - |
| dc.type.docType | Article; Proceedings Paper | - |
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