Digital clock data recovery circuit fot S/PDIF

Abstract

Clock data recovery (CDR) circuits are essential for serial data transmission such as wireless communications and Ethernet in order to read data by recovering and synchronizing the clock and by minimizing the effects of jitter. In this paper, we propose a digital CDR circuit with low output jitter and fast locking speed. The proposed CDR architecture consists of delayed line phase frequency detector, digital loop filter, divider, and digitally controlled oscillator. The proposed CDR circuit is designed using Verilog-HDL for S/PDIF, and is implemented by an automatic place and route (P&R) tool using UMC 55nm CMOS process. © 2016 IEEE.