Analysis of embedded-silicon-substrate impact on CiSP design

Abstract

This paper suggests routing design guides which help the lossy effect of an embedded silicon substrate be reduced in a chip-in-substrate package (CiSP). These guidelines are applied for determining optimal design of signal and power line. In order to achieve this purpose, the losses of a coplanar waveguide (CPW) line over an embedded silicon substrate and a ground plane are analyzed according to different position and length of the line. Also, via hole closed an embedded silicon substrate is analyzed with various height and distance to the embedded silicon substrate.