A product line engineering approach to designing System-on-Chips (SoC)
DC Field | Value | Language |
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dc.contributor.author | Chang, S.H. | - |
dc.contributor.author | Cheun, D.W. | - |
dc.contributor.author | Yu, T.K. | - |
dc.contributor.author | Kim, S.D. | - |
dc.date.available | 2019-04-10T11:41:25Z | - |
dc.date.created | 2018-04-17 | - |
dc.date.issued | 2006 | - |
dc.identifier.isbn | 9780889866072 | - |
dc.identifier.uri | http://scholarworks.bwise.kr/ssu/handle/2018.sw.ssu/33997 | - |
dc.description.abstract | System-on-Chip (SoC) technology enables implementing a fairly complex functionality in a small form-factor, and hence SoC becomes a key component of embedded systems. With the advances of semiconductor technology, the amount of functional features that a single SoC can embed increases sharply. Accordingly, the time and cost for developing SoCs are also increasing. A fundamental solution to manage the complexity is reuse engineering. Intellectual Property (IP) is a representative reuse approach; however, the reusability with IPs is limited to a relatively small grained functionality. As an effective reuse approach, product line engineering (PLE) is to capture common features among products into a core asset and to instantiate it for target products. In this paper, we propose a PLE-based process for designing SoC Our process is centered on modeling variability as well as commonality among a family of SoCs. Using the proposed process, SoCs can cost-effectively developed. | - |
dc.relation.isPartOf | Proceedings of the Fourth IASTED International Conference on Circuits, Signals, and Systems, CSS 2006 | - |
dc.title | A product line engineering approach to designing System-on-Chips (SoC) | - |
dc.type | Conference | - |
dc.type.rims | CONF | - |
dc.identifier.bibliographicCitation | 4th IASTED International Conference on Circuits, Signals, and Systems, CSS 2006, pp.175 - 180 | - |
dc.description.journalClass | 2 | - |
dc.identifier.scopusid | 2-s2.0-38349159577 | - |
dc.citation.conferenceDate | 2006-11-20 | - |
dc.citation.conferencePlace | San Francisco, CA | - |
dc.citation.endPage | 180 | - |
dc.citation.startPage | 175 | - |
dc.citation.title | 4th IASTED International Conference on Circuits, Signals, and Systems, CSS 2006 | - |
dc.contributor.affiliatedAuthor | Kim, S.D. | - |
dc.type.docType | Conference Paper | - |
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