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A Low-Loss On-Chip Transformer Using an Auxiliary Primary Part (APP) for CMOS Power Amplifier Applications

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dc.contributor.author임혜민-
dc.contributor.author박창근-
dc.date.available2019-07-12T07:20:33Z-
dc.date.created2019-07-12-
dc.date.issued2019-06-
dc.identifier.issn1226-7244-
dc.identifier.urihttp://scholarworks.bwise.kr/ssu/handle/2018.sw.ssu/34945-
dc.description.abstractWe propose a low-loss on-chip transformer using an auxiliary primary part (APP) for an output matchingnetwork for fully integrated CMOS power amplifiers. The APP is designed using a fifth metal layer while theprimary and secondary parts are designed using a sixth metal layer with a width smaller than that of theprimary and secondary parts of the transformer to minimize the substrate loss and the parasitic capacitancebetween the primary and secondary parts. By adapting the APP in the on-chip transformer, we obtain animproved maximum available gain value without the need for any additional chip area. The feasibility of theproposed APP structure is successfully verified.-
dc.language영어-
dc.language.isoen-
dc.publisher한국전기전자학회-
dc.relation.isPartOf전기전자학회논문지-
dc.titleA Low-Loss On-Chip Transformer Using an Auxiliary Primary Part (APP) for CMOS Power Amplifier Applications-
dc.typeArticle-
dc.identifier.doi10.7471/ikeee.2019.23.2.403-
dc.type.rimsART-
dc.identifier.bibliographicCitation전기전자학회논문지, v.23, no.2, pp.403 - 406-
dc.identifier.kciidART002483349-
dc.description.journalClass2-
dc.citation.endPage406-
dc.citation.number2-
dc.citation.startPage403-
dc.citation.title전기전자학회논문지-
dc.citation.volume23-
dc.contributor.affiliatedAuthor박창근-
dc.description.isOpenAccessN-
dc.subject.keywordAuthorCMOS-
dc.subject.keywordAuthorEfficiency-
dc.subject.keywordAuthorMagnetic coupling-
dc.subject.keywordAuthorMatching network-
dc.subject.keywordAuthorPower amplifier-
dc.subject.keywordAuthorTransformer-
dc.description.journalRegisteredClasskci-
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