HYFII: HYbrid Fault Injection Infrastructure for Accurate Runtime System Failure Analysis
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Jang, Sungmin | - |
dc.contributor.author | Park, Jaeyoung | - |
dc.date.available | 2020-11-16T05:41:49Z | - |
dc.date.created | 2020-11-03 | - |
dc.date.issued | 2020-08 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | http://scholarworks.bwise.kr/ssu/handle/2018.sw.ssu/39905 | - |
dc.description.abstract | In this article, we propose an efficient circuit reliability analysis infrastructure utilizing on-demand transistor-accurate fault injection based on workload-specific distributional properties. A novel two-phase approach is developed to achieve circuit-level accuracy, via careful transistor-level precharacterization, and gate-level efficiency, via fast runtime fault generation. A time-consuming circuit characterization is performed once, and the result of the precharacterization is used multiple times at runtime to inject faults. Also, novel fault probability estimation and fault injection methods are developed. Fault probabilities are computed based on workload-specific voltage/temperature distribution, and faults are injected efficiently by scaling the computed fault probabilities. We demonstrate the proposed methodology on an OpenSPARC core targeting an implementation on a 32-nm technology node. Analysis indicates that the injector computes the system failure rate with 0.1-ms simulation overhead per injection while having circuit-level accuracy. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.title | HYFII: HYbrid Fault Injection Infrastructure for Accurate Runtime System Failure Analysis | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/TVLSI.2020.2992982 | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.28, no.8, pp.1893 - 1900 | - |
dc.description.journalClass | 1 | - |
dc.identifier.wosid | 000554897100013 | - |
dc.citation.endPage | 1900 | - |
dc.citation.number | 8 | - |
dc.citation.startPage | 1893 | - |
dc.citation.title | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.citation.volume | 28 | - |
dc.contributor.affiliatedAuthor | Park, Jaeyoung | - |
dc.type.docType | Article | - |
dc.description.isOpenAccess | N | - |
dc.subject.keywordAuthor | Circuit faults | - |
dc.subject.keywordAuthor | Integrated circuit modeling | - |
dc.subject.keywordAuthor | Logic gates | - |
dc.subject.keywordAuthor | Analytical models | - |
dc.subject.keywordAuthor | Runtime | - |
dc.subject.keywordAuthor | Computational modeling | - |
dc.subject.keywordAuthor | Timing | - |
dc.subject.keywordAuthor | Circuit analysis | - |
dc.subject.keywordAuthor | circuit faults | - |
dc.subject.keywordAuthor | electrical fault detection | - |
dc.subject.keywordAuthor | failure analysis | - |
dc.subject.keywordAuthor | table lookup | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
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