Detailed Information

Cited 1 time in webofscience Cited 0 time in scopus
Metadata Downloads

HYFII: HYbrid Fault Injection Infrastructure for Accurate Runtime System Failure Analysis

Full metadata record
DC Field Value Language
dc.contributor.authorJang, Sungmin-
dc.contributor.authorPark, Jaeyoung-
dc.date.available2020-11-16T05:41:49Z-
dc.date.created2020-11-03-
dc.date.issued2020-08-
dc.identifier.issn1063-8210-
dc.identifier.urihttp://scholarworks.bwise.kr/ssu/handle/2018.sw.ssu/39905-
dc.description.abstractIn this article, we propose an efficient circuit reliability analysis infrastructure utilizing on-demand transistor-accurate fault injection based on workload-specific distributional properties. A novel two-phase approach is developed to achieve circuit-level accuracy, via careful transistor-level precharacterization, and gate-level efficiency, via fast runtime fault generation. A time-consuming circuit characterization is performed once, and the result of the precharacterization is used multiple times at runtime to inject faults. Also, novel fault probability estimation and fault injection methods are developed. Fault probabilities are computed based on workload-specific voltage/temperature distribution, and faults are injected efficiently by scaling the computed fault probabilities. We demonstrate the proposed methodology on an OpenSPARC core targeting an implementation on a 32-nm technology node. Analysis indicates that the injector computes the system failure rate with 0.1-ms simulation overhead per injection while having circuit-level accuracy.-
dc.language영어-
dc.language.isoen-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.relation.isPartOfIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS-
dc.titleHYFII: HYbrid Fault Injection Infrastructure for Accurate Runtime System Failure Analysis-
dc.typeArticle-
dc.identifier.doi10.1109/TVLSI.2020.2992982-
dc.type.rimsART-
dc.identifier.bibliographicCitationIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.28, no.8, pp.1893 - 1900-
dc.description.journalClass1-
dc.identifier.wosid000554897100013-
dc.citation.endPage1900-
dc.citation.number8-
dc.citation.startPage1893-
dc.citation.titleIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS-
dc.citation.volume28-
dc.contributor.affiliatedAuthorPark, Jaeyoung-
dc.type.docTypeArticle-
dc.description.isOpenAccessN-
dc.subject.keywordAuthorCircuit faults-
dc.subject.keywordAuthorIntegrated circuit modeling-
dc.subject.keywordAuthorLogic gates-
dc.subject.keywordAuthorAnalytical models-
dc.subject.keywordAuthorRuntime-
dc.subject.keywordAuthorComputational modeling-
dc.subject.keywordAuthorTiming-
dc.subject.keywordAuthorCircuit analysis-
dc.subject.keywordAuthorcircuit faults-
dc.subject.keywordAuthorelectrical fault detection-
dc.subject.keywordAuthorfailure analysis-
dc.subject.keywordAuthortable lookup-
dc.relation.journalResearchAreaComputer Science-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalWebOfScienceCategoryComputer Science, Hardware & Architecture-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
Files in This Item
There are no files associated with this item.
Appears in
Collections
College of Information Technology > ETC > 1. Journal Articles

qrcode

Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.

Altmetrics

Total Views & Downloads

BROWSE