BitBlade: Energy-Efficient Variable Bit-Precision Hardware Accelerator for Quantized Neural Networks
DC Field | Value | Language |
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dc.contributor.author | Ryu, Sungju | - |
dc.contributor.author | Kim, Hyungjun | - |
dc.contributor.author | Yi, Wooseok | - |
dc.contributor.author | Kim, Eunhwan | - |
dc.contributor.author | Kim, Yulhwa | - |
dc.contributor.author | Kim, Taesu | - |
dc.contributor.author | Kim, Jae-Joon | - |
dc.date.accessioned | 2022-02-22T07:40:02Z | - |
dc.date.available | 2022-02-22T07:40:02Z | - |
dc.date.created | 2022-02-22 | - |
dc.date.issued | 2022-06 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://scholarworks.bwise.kr/ssu/handle/2018.sw.ssu/41722 | - |
dc.description.abstract | We introduce an area/energy-efficient precisionscalable neural network accelerator architecture. Previous precision-scalable hardware accelerators have limitations such as the under-utilization of multipliers for low bit-width operations and the large area overhead to support various bit precisions. To mitigate the problems, we first propose a bitwise summation, which reduces the area overhead for the bit-width scaling. In addition, we present a channel-wise aligning scheme (CAS) to efficiently fetch inputs and weights from on-chip SRAM buffers and a channel-first and pixel-last tiling (CFPL) scheme to maximize the utilization of multipliers on various kernel sizes. A test chip was implemented in 28-nm CMOS technology, and the experimental results show that the throughput and energy efficiency of our chip are up to 7.7x and 1.64x higher than those of the state-of-the-art designs, respectively. Moreover, additional 1.5-3.4x throughput gains can be achieved using the CFPL method compared to the CAS. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.relation.isPartOf | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.title | BitBlade: Energy-Efficient Variable Bit-Precision Hardware Accelerator for Quantized Neural Networks | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/JSSC.2022.3141050 | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.57, no.6, pp.1924 - 1935 | - |
dc.description.journalClass | 1 | - |
dc.identifier.wosid | 000748324200001 | - |
dc.identifier.scopusid | 2-s2.0-85123683357 | - |
dc.citation.endPage | 1935 | - |
dc.citation.number | 6 | - |
dc.citation.startPage | 1924 | - |
dc.citation.title | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.citation.volume | 57 | - |
dc.contributor.affiliatedAuthor | Ryu, Sungju | - |
dc.type.docType | Article | - |
dc.description.isOpenAccess | N | - |
dc.subject.keywordAuthor | Computer architecture | - |
dc.subject.keywordAuthor | Neural networks | - |
dc.subject.keywordAuthor | Hardware acceleration | - |
dc.subject.keywordAuthor | Adders | - |
dc.subject.keywordAuthor | Arrays | - |
dc.subject.keywordAuthor | Random access memory | - |
dc.subject.keywordAuthor | Throughput | - |
dc.subject.keywordAuthor | Bit-precision scaling | - |
dc.subject.keywordAuthor | bitwise summation | - |
dc.subject.keywordAuthor | channel-first and pixel-last tiling (CFPL) | - |
dc.subject.keywordAuthor | channel-wise aligning | - |
dc.subject.keywordAuthor | deep neural network | - |
dc.subject.keywordAuthor | hardware accelerator | - |
dc.subject.keywordAuthor | multiply-accumulate unit | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
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