High-throughput Near-Memory Processing on CNNs with 3D HBM-like Memory
- Authors
- Park, N.; Ryu, S.; Kung, J.; Kim, J.-J.
- Issue Date
- Jun-2021
- Publisher
- Association for Computing Machinery
- Keywords
- HBM; Neural network accelerator
- Citation
- ACM Transactions on Design Automation of Electronic Systems, v.26, no.6
- Journal Title
- ACM Transactions on Design Automation of Electronic Systems
- Volume
- 26
- Number
- 6
- URI
- http://scholarworks.bwise.kr/ssu/handle/2018.sw.ssu/41724
- DOI
- 10.1145/3460971
- ISSN
- 1084-4309
- Abstract
- This article discusses the high-performance near-memory neural network (NN) accelerator architecture utilizing the logic die in three-dimensional (3D) High Bandwidth Memory- (HBM) like memory. As most of the previously reported 3D memory-based near-memory NN accelerator designs used the Hybrid Memory Cube (HMC) memory, we first focus on identifying the key differences between HBM and HMC in terms of near-memory NN accelerator design. One of the major differences between the two 3D memories is that HBM has the centralized through-silicon-via (TSV) channels while HMC has distributed TSV channels for separate vaults. Based on the observation, we introduce the Round-Robin Data Fetching and Groupwise Broadcast schemes to exploit the centralized TSV channels for improvement of the data feeding rate for the processing elements. Using synthesized designs in a 28-nm CMOS technology, performance and energy consumption of the proposed architectures with various dataflow models are evaluated. Experimental results show that the proposed schemes reduce the runtime by 16.4-39.3% on average and the energy consumption by 2.1-5.1% on average compared to conventional data fetching schemes. © 2021 Association for Computing Machinery.
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