Low-overhead, one-cycle timing-error detection and correction technique for flip-flop based pipelines

Abstract

We propose a low-overhead, one-cycle timing-error detection and correction (EDAC) technique for flip-flop based pipelines. In order to prevent data collision during local clock gating for rapid error correction, the proposed technique performs clock gating of the master and the slave latches inside the flip-flops independently. Unlike previous flip-flop based one-cycle EDAC techniques, the independent clock gating in the proposed technique enables selective replacement of EDAC flip-flops, thereby reducing the area and power consumption overhead. Our experiments using a 3-stage pipeline consisting of 8-bit multipliers showed that the proposed technique improved the area and power consumption by 66% and 88%, respectively, compared to the state-of-the-art flip-flop based EDAC technique while showing a comparable area and power consumption with the two-phase latch based EDAC technique. A 32-bit, 5-stage MIPS microprocessor data path testchip based on the proposed technique was implemented in a 65 nm CMOS technology. With the proposed one-cycle EDAC technique, the silicon measurement results from 31 dies showed 24.3% higher throughput and 8.7% less energy consumption beyond the point of the first failure (PoFF).