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수정된 의사 무작위 패턴을 이용한 효율적인 로직 내장 자체 테스트에 관한 연구
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이정민;
장훈
Article
Issue Date
2006
Citation
전자공학회논문지 - SD, v.43, no.8, pp.27 - 34
Publisher
대한전자공학회
그라운드 바운스 영향과 지연고장을 위한 최소화된 테스트 패턴 생성 기법
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김문준;
장훈
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Issue Date
2004
Citation
전자공학회논문지 - SD, v.41, no.11, pp.1033 - 1042
Publisher
대한전자공학회
고장 모델 기반 메모리 BIST 회로 생성 시스템 설계
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장훈
; 심은성
Article
Issue Date
2005
Citation
전자공학회논문지 - SD, v.42, no.2, pp.127 - 134
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대한전자공학회
SRAM 이중-포트를 위한 내장된 메모리 BIST IP 자동생성 시스템 개발
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심은성;
장훈
; 이정민; 이찬영
Article
Issue Date
2005
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전자공학회논문지 - SD, v.42, no.2, pp.135 - 142
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