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Cited 11 time in webofscience Cited 21 time in scopus
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The Optimal Design of Junctionless Transistors with Double-Gate Structure for reducing the Effect of Band-to-Band Tunneling

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dc.contributor.authorWu, Meile-
dc.contributor.authorJin, Xiaoshi-
dc.contributor.authorKwon, Hyuck-In-
dc.contributor.authorChuai, Rongyan-
dc.contributor.authorLiu, Xi-
dc.contributor.authorLee, Jong-Ho-
dc.date.available2019-03-09T01:57:24Z-
dc.date.issued2013-06-
dc.identifier.issn1598-1657-
dc.identifier.urihttps://scholarworks.bwise.kr/cau/handle/2019.sw.cau/14623-
dc.description.abstractThe effect of band-to-band tunneling (BTBT) leads to an obvious increase of the leakage current of junctionless (JL) transistors in the OFF state. In this paper, we propose an effective method to decline the influence of BTBT with the example of n-type double gate (DG) JL metal-oxide-semiconductor field-effect transistors (MOSFETs). The leakage current is restrained by changing the geometrical shape and the physical dimension of the gate of the device. The optimal design of the JL MOSFET is indicated for reducing the effect of BTBT through simulation and analysis.-
dc.format.extent7-
dc.language영어-
dc.language.isoENG-
dc.publisherIEEK PUBLICATION CENTER-
dc.titleThe Optimal Design of Junctionless Transistors with Double-Gate Structure for reducing the Effect of Band-to-Band Tunneling-
dc.typeArticle-
dc.identifier.doi10.5573/JSTS.2013.13.3.245-
dc.identifier.bibliographicCitationJOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.13, no.3, pp 245 - 251-
dc.identifier.kciidART001774932-
dc.description.isOpenAccessN-
dc.identifier.wosid000322674800008-
dc.identifier.scopusid2-s2.0-84878842858-
dc.citation.endPage251-
dc.citation.number3-
dc.citation.startPage245-
dc.citation.titleJOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE-
dc.citation.volume13-
dc.type.docTypeArticle-
dc.publisher.location대한민국-
dc.subject.keywordAuthorBand-to-band tunneling (BTBT)-
dc.subject.keywordAuthordouble-gate (DG)-
dc.subject.keywordAuthorjunctionless field-effect transistor (JL FET)-
dc.subject.keywordAuthordevice simulation-
dc.subject.keywordAuthoroptimal design-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalResearchAreaPhysics-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.relation.journalWebOfScienceCategoryPhysics, Applied-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.description.journalRegisteredClasskci-
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