Bias-Stress-Induced Instabilities in P-Type Cu2O Thin-Film Transistors
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Park, Ick-Joon | - |
dc.contributor.author | Jeong, Chan-Yong | - |
dc.contributor.author | Myeonghun, U. | - |
dc.contributor.author | Song, Sang-Hun | - |
dc.contributor.author | Cho, In-Tak | - |
dc.contributor.author | Lee, Jong-Ho | - |
dc.contributor.author | Cho, Eou-Sik | - |
dc.contributor.author | Kwon, Hyuck-In | - |
dc.date.available | 2019-03-09T01:58:44Z | - |
dc.date.issued | 2013-05 | - |
dc.identifier.issn | 0741-3106 | - |
dc.identifier.issn | 1558-0563 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/cau/handle/2019.sw.cau/14674 | - |
dc.description.abstract | We investigate the gate bias-stress-induced instabilities of p-type copper oxide (Cu2O) thin-film transistors (TFTs). Transfer curves measured before and after the application of constant gate bias stress under air and vacuum environments show that the partial pressure of the oxygen in the environment does not much affect the transfer characteristics and bias-stress-induced instabilities of the Cu2O TFTs. During the negative gate bias stresses, the transfer curves shift to the negative direction without a significant variation of the shape, which is attributed to the hole trapping in the interface or bulk dielectric layers with a negligible creation of additional interface trap states. During the positive gate bias stresses, a threshold voltage hardly moves to the positive direction because of the lack of free electron inside the p-type Cu2O, but a notable degradation of the subthreshold slope is observed. From the recovery characteristics, the generated traps during the positive gate bias stress are estimated to be metastable ones in p-type Cu2O TFTs. | - |
dc.format.extent | 3 | - |
dc.language | 영어 | - |
dc.language.iso | ENG | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Bias-Stress-Induced Instabilities in P-Type Cu2O Thin-Film Transistors | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/LED.2013.2253758 | - |
dc.identifier.bibliographicCitation | IEEE ELECTRON DEVICE LETTERS, v.34, no.5, pp 647 - 649 | - |
dc.description.isOpenAccess | N | - |
dc.identifier.wosid | 000318433400025 | - |
dc.identifier.scopusid | 2-s2.0-84876956639 | - |
dc.citation.endPage | 649 | - |
dc.citation.number | 5 | - |
dc.citation.startPage | 647 | - |
dc.citation.title | IEEE ELECTRON DEVICE LETTERS | - |
dc.citation.volume | 34 | - |
dc.type.docType | Article | - |
dc.publisher.location | 미국 | - |
dc.subject.keywordAuthor | Bias-stress-induced instability | - |
dc.subject.keywordAuthor | charge trapping | - |
dc.subject.keywordAuthor | p-type copper oxide (Cu2O) thin-film transistors (TFTs) | - |
dc.subject.keywordAuthor | trap state creation | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | sci | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
84, Heukseok-ro, Dongjak-gu, Seoul, Republic of Korea (06974)02-820-6194
COPYRIGHT 2019 Chung-Ang University All Rights Reserved.
Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.